SDR1000 DDS Phase Noise Measurements

Lets take a look at the output of the synthesizer. The DDS chip
(AD9854) in the SDR contains its own reference multiplier. By
setting the multiplier to 20 in the SDR software a 10 MHz
oscillator can be used as the reference clock. As previously
stated, multiplying the reference degrades its phase noise.
Conversely, division improves it by the same factor. One would
expect the 10 MHz output to be nearly identical to the 10 MHz
OCXO input. The circled area of the blue trace deviates from
theory. See figure 7.

The circled area on the red trace of the DDS output, fed from the
VF161, has the same amount of noise at the 10 MHz output as at
the 200 MHz input! See the next figure.

This I did not expect! Figure 6 shows the VF161 phase noise at
200 MHz and the DDS output at 10 MHz. I expected the 10 MHz
phase noise to approach values 26 dB lower at all offsets. Since
I measured the VF161 phase noise in a fixture there may be an
interface issue in the SDR that degrades the oscillator. Further
investigation is warranted.

Figure 7 shows 10 MHz into and out of the DDS. Below 10 Hz
offset it actually looks cleaner. Out at 50 KHz its about 35dB
worse. What’s going on? Bad measurement, theory?

This data supports what was observed with the OCXO. Here the
oscillator is a TCXO. The hump at 1000 Hz is very familiar to PLL
designers. In a PLL, within the loop bandwidth the phase noise
takes on the characteristics of the reference crystal. Farther
out, the phase noise is dictated by the VCO. As it turns out the
DDS chip uses a PLL to multiply the reference! Bad news. At 11
KHz offset there is an opportunity to gain nearly a 35 dB
improvement in noise performance.

Changing the output frequency varies the position of the spurs
relative to the center frequency. Fortunately the DDS artifacts
are quite predictable. The SDR utilizes a common technique that
shifts the LO frequency to place the spurs outside the selected
pass band and then offsets the detector for correct demodulation.

Figures 10 & 11 show that the phase noise decreases as the DDS
frequency is lowered. In these examples, -20log(5) or –14dB.

The phase noise performance the VF161 compares favorably with other quality crystal
oscillators. Close in phase noise performance of the 200 MHz oscillator does not yield
the 20log(N) improvement at the DDS output.   Further investigation is required.

A quality 10 MHz reference shows significant close in performance gains. The DDS
internal reference multiplier unfortunately limits phase noise performance past 100 Hz
to –120dBc. An external multiplier could provide more than a 30dB improvement in this
area. Another possibility is to open up the loop BW of the DDS PLL multiplier (pin 61)
to push the hump past 15 KHz.

All Phase Noise Measurements were made on the New 
Agilent Technologies E5052A Signal Source Analyzer